1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to controlling the placement and manufacture of gate electrodes in semiconductor devices.
2. Description of the Related Art
As semiconductor device sizes are scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. As device sizes shrink, increasingly complex etch processes are used to define semiconductor devices features, such as polysilicon gates, in close proximity to one another. The same density motivations apply in using MOS transistor devices to design logic devices so that more logic devices are placed on smaller and smaller areas.
Accordingly, a need exists for a semiconductor manufacturing process which provides better control of the fabrication and placement of gate electrodes. In addition, there is a need for a fabrication process which uses MOS transistor devices to form smaller logic components. There is also a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.